🚀 go-pugleaf

The performance of the new machines announced by DEC on some
on the SPECfp92 programs, more specifically alvinn and ear,
is quite impressive.

Some of the performance can be explained by the size of the external
cache, which is 4 Mbytes per cpu for the mainframe-class machines,
but that alone doesn't explain all the gains (vs. similar processors).

First let's look at the difference between the low-end (133 MHz),
an hypothetical low-end scaled to 200 MHz and the one-processor
mainframe (200 MHz with large external cache):

Machine.......:    A		    B		   C
Model.........:	3000/400	hypothetical	10000/610
clock.........:	133 MHz		200 MHz		200 MHz
External Cache:	512K		4M		4M

		(SPECratios)
benchmark:	alvinn	ear
machine A:	263.6	397.1
machine B:	396.4	597.1
machine C:	502.9	605.7
improv (C/B)	27%	56%

I assume that most of the improvement from machine B to machine C
comes from the external cache size. Maybe someone from DEC could
comment on the latency of the various external caches?
Does the external cache on the 200 MHz machine have the minimum
3-cycle latency?

Now, let's compare machine B with an hypothetical 200 MHz HP machine.
The numbers I will use are from the 100 MHz (really 99 MHz)
HP machine recently announced scaled to a 200 MHz machine.

Machine.......:    D
Model.........:	HP/hypothetical
clock.........:	200 MHz
Cache (I+D)...:	512K

		(SPECratios)
benchmark:	alvinn	ear
machine B	396.4	597.1
machine D	353.8	516.8
improv (B/D)	10.6%	15.5%
  
Considering that this hypothetical HP machine has 2 cycle latency
floating-point operations, much closer caches, muladd capabilities,
smaller mispredicted branch penalty, etc., these numbers are quite
surprising. They represent a swing of maybe 30% in the opposite 
direction. DEC must be doing something pretty fancy with their
compilers. Could someone from DEC comment on what kind of
optimizations were used on alvinn and ear?

Thanks,

- Marc Tremblay.
Sun Microsystems.