🚀 go-pugleaf

In article endecotp@cs.man.ac.uk writes:
>Although it's true that both register+offset and register+register modes
>require an addition, you haven't allowed for the fact that an extra
>register read has to take place.  Normally most microprocessors have two
>read ports and one write port on the register file, which is exactly what
>is required for three address arithmetic/logical operations.  When you
>execute a store instruction, one read port is used for the data value, and
>the other for the address register.

Actually most microprocessors these days have a register file with many ports.
All major companies (DEC, HP, Intel, Sun, Motorola, SGI, etc), are developing
superscalar processors which require many ports.
Adding one read port for allowing the loads to use the register+register
addressing mode becomes a smaller overhead as a percentage of the (bigger)
register file. If you look at the layout of some of these chips you will
see that the register file represents a small part of the die.
Considering that this addressing mode can lead to saving an instruction
(addition), it can be a real advantage.

Here is the percentage of loads and stores for SPECint92 benchmarks
running on SPARC which use the two register addressing mode [RX + RY]:

benchmark	loads	stores
---------	-----	------
espresso	37%	9.8%
li		2.5%	2.8%
eqntott		76.4%	5.4%
compress	27%	7.3%
sc		13.5%	7.9%
gcc		18.9%	37.5%

The numbers show that the compiler (based on SunPro SC2.0.1) makes
good use of this capability. There are ways around this addressing mode,
but a significant portion of the above percentage do save an addition.

If there is interest I can look into the numbers for floating-point code.

- Marc Tremblay.
Sun Microsystems.