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Article #8003Re: MIPS and MHz
From: Donald Lindsay
Date: Thu, 12 Nov 1992 23:39
Date: Thu, 12 Nov 1992 23:39
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NetCmmnd@boole.uucp (System Administrator) writes: >How can a non-superscalar implementation at 50MHz run 59.1 MIPS? >I thought the holy grail of RISC was 1 instruction retired per cycle >and that this is never attained (much less exceeded) in a non- >superscalar implementation. Correct, for reasonable measures of MIPS. However, "Dhrystone 1.1 MIPS" have ceased to be reasonable. The "MIPS" is calculated by assuming that the VAX 11/780 was 1 MIPS, and then taking an execution-time ratio versus a historical VAX value. As compilers have improved (and have acquired Dhrystone-1.1-specific optimizations), the D-MIPS ratings have inflated beyond reason. -- Don D.C.Lindsay Carnegie Mellon Computer Science
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Path: arc1-ca.pugleaf.net!sparky!uunet!ogicse!das-news.harvard.edu!cantaloupe.srv.cs.cmu.edu!lindsay From: lindsay+@cs.cmu.edu (Donald Lindsay) Newsgroups: comp.arch Subject: Re: MIPS and MHz Keywords: RISC, MIPS, cps Message-ID: <BxMn1J.GB3.2@cs.cmu.edu> Date: 12 Nov 92 23:39:18 GMT Article-I.D.: cs.BxMn1J.GB3.2 References: <1992Nov12.183424.29331@boole.uucp> Sender: news@cs.cmu.edu (Usenet News System) Organization: School of Computer Science, Carnegie Mellon Lines: 16 Nntp-Posting-Host: gandalf.cs.cmu.edu