🚀 go-pugleaf

In article <1992Oct31.000805.2898@sics.se>, craig@sics.se (Craig Partridge) writes:
|> 
|> Hi:
|> 
|> Here's a futuristic question I'm puzzling over.
|> 
|> It has been asserted that there's an impending fiber/silicon bottleneck
|> in data communications.  The argument says, in short, that we can signal
|> far faster in a fiber than we can hope to get the electronics going in
|> silicon, and we have to study that problem.  So I'm polling this group
|> of silicon experts to see what you think.
|> 
|> At its very best (wind-aided, etc.) a fiber could conceivably achieve a
|> transmission 40 terabits/second (40 Thz).  My understanding is that the
|> key problem is figuring out how to clock bits that fast into silicon.
|> 
|> My immediate reaction is that I would expect there might be some way to
|> make this fly.  For example, 1 terabit per second, on an 128-bit wide
|> bit path is about a 0.1 ns clock cycle, which is only a modest improvement
|> over what DEC reputedly hopes to achieve for Alpha clock cycles in the
|> future.  Now going serial to parallel would presumably require some pico-second
|> logic somewhere, but maybe that's possible.

I would suggest that there are two problems with this method of figuring.

1) The terabit per second firgure that is creating the bottleneck is in a
single fiber. Your clock rate will have to be determined for a 1 bit wide
path. Then you get a 1 ps clock. Even SFQ logic won't do that.

2) You have either accidentally decided to believe DEC marketing propaganda
that claims that they will be clocking Si circuits at 10 GHz, or the 10 GHz
figure is what they expect the Alpha architecture to be clocked at at the end
of its lifetime which, in an atempt to bring a little humor into all of our
lives, has been estimated at about 25 years.

Jason W. Solinsky