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Article #8021

Re: 600 transistor CPU (was: MINIMUM instruction set)

#8021
From: Charles Perkins
Date: Fri, 13 Nov 1992 16:04
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In article <1992Nov13.104602.10923@odin.diku.dk> torbenm@diku.dk (Torben AEgidius Mogensen) writes:
>caperkin@ursa11.law.utah.edu (Charles Perkins) writes:
>
>>This caught my attention because of an idea I have been toying with, which
>>I have decided to call the Fractal Logic Asynchronous Scalable Circuit.
>>(Basically a 'memory' where every cell is a finite state autonoma 'conversing'
>>with the cells next to it.)  I figure eight thousand of the little guys on a 
>>chip, simple though they might be individually, could get some serious
>>computation done.
>
>Have you considered how to program such a beast? And on the hardware
>side, how do you load a program?
>
>	Torben Mogensen (torbenm@diku.dk)

It wouldn't be in C.

Actually, the whole idea is to break out of the VN bottleneck.
I imagine the architecture would be best suited to a wierd variant of prolog.
Each cell, when queried, could (hypothetically) either return it's value
(true or false) or (in conjunction with cells next to it) query other cells
to determine what it's value ought to be, then report that.

Thus there would be facts and rules.  The more complicated a query, the more
branching and parallel action occurs.  (The organization of the cells
would also follow a tree structure, rather than a linear or array structure,
for several reasons.  The main reason being the 'Scalable' in the acronym.)

Programming would be through set, rather than query location.

I would hate to port X to it, though.

-- 
 .8Chuck .2AlexanderGrahmBell
 perkins@ursa11.law.utah.edu
 "I am not a potted plant."
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Message-ID: <1992Nov13.160442.9619@fcom.cc.utah.edu>
Path: arc1-ca.pugleaf.net!sparky!uunet!charon.amdahl.com!pacbell.com!decwrl!concert!gatech!news.byu.edu!ux1!fcom.cc.utah.edu!ursa11.law.utah.edu!caperkin
References: <1992Nov12.164510.28248@dartvax.dartmouth.edu> <1992Nov12.220301.23915@fcom.cc.utah.edu> <1992Nov13.104602.10923@odin.diku.dk>

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From: caperkin@ursa11.law.utah.edu (Charles Perkins)
Subject: Re: 600 transistor CPU (was: MINIMUM instruction set)
Message-ID: <1992Nov13.160442.9619@fcom.cc.utah.edu>
Summary: Program the FLASC?
Sender: Charles A. Perkins
Organization: University of Utah College of Law
References: <1992Nov12.164510.28248@dartvax.dartmouth.edu> <1992Nov12.220301.23915@fcom.cc.utah.edu> <1992Nov13.104602.10923@odin.diku.dk>
Date: Fri, 13 Nov 92 16:04:42 GMT
Lines: 36