🚀 go-pugleaf

In <BxMn1J.GB3.2@cs.cmu.edu> lindsay+@cs.cmu.edu (Donald Lindsay) writes:

>NetCmmnd@boole.uucp (System Administrator) writes:
>>How can a non-superscalar implementation at 50MHz run 59.1 MIPS?
>>I thought the holy grail of RISC was 1 instruction retired per cycle
>>and that this is never attained (much less exceeded) in a non-
>>superscalar implementation.

>Correct, for reasonable measures of MIPS.

>However, "Dhrystone 1.1 MIPS" have ceased to be reasonable.  The
>"MIPS" is calculated by assuming that the VAX 11/780 was 1 MIPS, and
>then taking an execution-time ratio versus a historical VAX value.

>As compilers have improved (and have acquired Dhrystone-1.1-specific
>optimizations), the D-MIPS ratings have inflated beyond reason.
>-- 
>Don		D.C.Lindsay 	Carnegie Mellon Computer Science

Not only that but the 11/780 was a .5 MIPS machine
and NOWHERE IN THE STUFF from Sun that I saw was there
any mention of "Dhrystone MIPS" or what they are or 
how they are calculated.  

John Ahlstrom
Boole & Babbage

I can neither confirm nor deny that
these opinions are held by anyone elsee