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Article #1668Re: Info on DSP chips
From: Bill Smith
Date: Wed, 26 Jul 1989 19:24
Date: Wed, 26 Jul 1989 19:24
43 lines
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2761 bytes
In article <23379@winchester.mips.COM>, mash@mips.COM (John Mashey) writes: > In article <337@venus.iotek.UUCP> garyb@iotek.UUCP (Gary R. Burrell) writes: > > >IEEE Micro December 1988 > > > > A Special Issue on DSP processors, contains detailed articles > >on the TMS320C30, DSP32c and DSP96002. These are fairly good articles > >about the various DSP processors. The only part of the issue I really > >question is the editors afterword in which they come up with some > >amazing figures for Linpack ratings of the TMS320C30 (20 MFLOPS) and > >DSP96000 (30 MFLOPS). I question these ratings as most supercomputers > >only get about 1/10 of there peak performance rating on the LINPACK > >benchmark. > I conjecture that what they must mean is the inner-loop timing for > the standard LINPACK code, but with zero-wait-state memory, > i.e., something not particularly buildable. To be fair, it is not > unreasonable to quote such numbers, if they are clearly labeled as such, > because a chip vendor can't control what they're put into, > although it would be more meaningful to quotethem with a specified memory > system of course. > -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> Sorry this is so late a followup. I haven't seen the article under discussion nor information about the DSP chips except the TMS320C30, and that information may invalidates John Mashey's comments. The TMS320C30 has a fairly large amount of program space on chip (something like 4k words) that is zero-wait state and probably also multi-ported (but I might be getting the register file confused with the memory buffers). If the inner loops fit within the on-chip memory or can be paged in and out with the on-chip DMA logic, the TMS320C30 can do some pretty amazing things. The other chips may also have similarly sophisticated architectures, but I'm not sure. (In case you can't tell, I like the TMS320x0 chips.) Don't incriminate a vendor about flakey benchmark numbers without verifying that the benchmarks are in fact flakey (which I haven't actually done, but...) Bill Smith pur-ee!mdbs!wsmith (A long time ago in a universe far far away, I was wsmith@cs.uiuc.edu, but no longer :-)
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!usc!cs.utexas.edu!tut.cis.ohio-state.edu!purdue!mentor.cc.purdue.edu!pur-ee!pur-phy!sawmill!mdbs!wsmith From: wsmith@mdbs.UUCP (Bill Smith) Newsgroups: comp.arch,comp.misc Subject: Re: Info on DSP chips Summary: TMS32030 have a bunch of zero wait state memory on chip Message-ID: <1451@mdbs.UUCP> Date: 26 Jul 89 19:24:09 GMT References: <337@venus.iotek.UUCP> <23379@winchester.mips.COM> Organization: MDBS Inc., Lafayette, IN Lines: 43