🚀 go-pugleaf

In article <1430@navajo.STANFORD.EDU> billw@navajo.STANFORD.EDU (William E. Westfield) writes:
>
>So has anyone done research to see if it might be worthwhile to
>implement a machine with multiple sets of registers (say 16 sets
>of 64 registers, with register windows)?

The Celerity Accel processor in the C1200 series has implemented exactly
this approach: a two-dimensional register stack cache, one dimension being
the sliding-window implementation, the second dimension being an index by
context ID, allowing bank-switching and fast context switch between most
active processes.  The register configuration is as follows:

Each window is composed of 16 parameter registers, 16 local variable
registers, and a window into the next 16 registers (a callee's parameter
registers).  Registers are configured as follows on each model:

Model         Number of windows (depth)     Number of contexts (width)
=====         =========================     ==========================

C1200                  16                             8
C1230                  32                            16
C1260 Dyadic           32                            32 (16 per processor)

The Extended Arithmetic Unit tightly coupled co-processor also has its
own stack cache of 64-bit registers: 15 frames of 15 64-bit registers
on the C1200, 8 banks of 15 frames of 15 64-bit registers on the C1230,
and 8 banks of 15 frames of 15 on the C1260.  (The more observant of you
might have guessed that the C1260 is a symmetrical dual processor based
on the C1230...)

Use of static, on-chip registers to augment the register stack caches has
been discussed earlier in this group by JJ Whelan of Celerity's engineering
group, who is a more informed speaker than I (but I'm in Sales Support, so
I just love to shoot my mouth off... :-)

-- 
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///        Roger B.A. Klorese, CELERITY (Northeast Area)
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