🚀 go-pugleaf

I worked on Josephson junction logic gates 10 years ago.  I work on
silicon now.  Some comments on JJs in computers:

Advantages:
   JJ's prime advantage is their very low power,  allowing them to be placed
closely together.  With proper design, you can design JJ gates with switch
energies of just a few kT.  JJ gates can be made to match transmission lines
 - hard to do at low power with semiconductor circuits requiring >100mV
logic swings.  At liquid helium temperatures, it's possible to use superfluid
effects in the LHe to cool them, allowing 3D stacking of die.  Imagine a
CRAY, 100x speed, a centimeter on a side (You've heard THAT one before, I'll
guess!).  Just don't ask how to build it!

   Given a computer that consumes milliwatts, the cooling problem is
simplified, even with Carnot efficiencies included.  What is the biggest
box in YOUR computer center?  Ours says "Liebert".

   In all the LSI random logic systems I've seen, the active area of the
chip is a fraction of a percent, the rest being interconnect.  Imagine
what superconducting transmission lines can do for you here (Note:
superconducting wires are still dispersive - at a Terahertz or so).

   There is a lot of room for improvement in circuit design.  With proper
design and close attention to device matching, a JJ circuit shouldn't
be much harder to design than an NMOS circuit.  While some things are
looser, such as junction critical currents, other things like 2e/h 
seem pretty well under control.  Proper circuit design (which IBM 
didn't appear to understand) relies on those things that are easy
to control, and matches out or designs around hard-to-control parameters,
and avoids dependence on too may of them (such as the gap voltage).

Disadvantages:
   JJs are W*E*I*R*D.  You need new test equipment, design tools,
manufacturing equipment and techniques.  GaAs has problems with its
special equipment requirements;  imagine the problems with JJ.  JJs
don't benefit much from the billions spent in silicon R&D that
eventually ends up in consumer and military equipment.  However, this isn't
stopping Fujitsu, who just built a 16 bit ALU slice with JJ technology.
I hope American manufacturers don't find themselves on the wrong side
of a huge technological barrier.  Even on the right side, we can't always
keep up with Asia.

  Interconnect with the "real world" is a problem.  The signals are small
and fast.  Testing is a similar problem, although Hypress sampling
technology can be used, completely in the dewar at low temp.  Not cheap
or easy, though, and not off-the-shelf technology.

  Design is odd!  Ever tried using Kirchoff's law for quantum mechanical
phase?  With speed-of-light and unpaired electron currents and flux
pinning and wave interference thrown in?  Not harder, but very different.
When the circuits get fast enough, quantization of the signals themselves
(Your logic signals become packets of milli-electron-volt energy) may
become a problem.

  The inconvenience of temperature cycling changes test philosophies.
Built-In-Self-Test is a MUST.  Redundancy would be very useful.  Thermally
activated failures such as electromigration and junction leakage are absent,
but vibration and ESD may still reach inside the dewar,  so "board-swapping"
may still be necessary. IBM had a lead junction process that could stand
temp cycling, and the Fujitsu Niobium/Aluminum Oxide process should be
even more robust.  I would worry about connections unmating, though, which
is where I'd put the redundancy.

Conclusions:
   It's a lot of work.  The engineering probably costs more than other
alternatives such as massive parallelism, which should be developed first.
But when those schemes hit the wall (and on some problems they will),
JJs may be the way out.  Don't sell your Niobium mining stock yet :-)



-- 
Keith Lofstrom
MS 59-316, Tektronix, PO 500, Beaverton OR 97077  (503)-627-4052