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The i486 handles misaligned transfers transparently from the programming 
standpoint.  From a performance standpoint, there is no penalty for aligned 
transfers, for misaligned transfers a misaligned transfer adds two
clocks to the two transfers that need to be performed to get the data.
Thus, for all cache hits, an aligned load takes 1 clock while a misaligned
load takes 4 clocks (2 + 1 for each transfer).  The two clocks are a "false
start clock" for the transfer that gets aborted (since split processing is
required) and a "tickle" cycle that insures that before any data transfer is
attempted that the whole object is addressable.  Thus, no transfer for a
memory object will be seen on the pins until the processor has determined
that it can retrieve both parts.

In addition, the i486 has the ability to force traps on all misaligned
transfers.  This lets people insure that the data structures for their
programs are such that they are getting the highest performance from their
machines and also insures that their data structures are portable with
mathines that don't support misaligned transfers (assuming, of course, that
the hardware supported representation of objects is the same in memory).
This facility is provided through a bit in control register 0, which, by
default, allows misaligned objects.
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Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California
csnet/arpanet: kds@mipos2.intel.com
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