🚀 go-pugleaf

In article <10544@cit-vax.Caltech.Edu> yair@tybalt.caltech.edu.UUCP (Yair Zadik) writes:
>A couple of years ago there was an article in Byte about a proposed design
>which they called WISC for Writeable Instruction Set Computer.  The idea
>was to do a RISC or microcoded processor which had an on board memory 
>containing macros which behaved like normal instructions (I guess it was
>on EEPROM like memory).  That way, each compiler could optimize the 
>instruction set for its language.  The end result (theoreticly) is that
>you get the efficiency of RISC with the memory bandwith of CISC.  I haven't
>heard else about it.  Is anyone out there working on such a processor or is
>it just a bad idea?
>
>Yair Zadik
>yair@tybalt.caltech.edu

The only problem with this is that doing a context switch is nearly impossible.
Imagine not only saving registers but having to swap out microcode and
instructions too.  Not to mention that porting a compiler to do this might be
a lot harder.  Portability would be sure to take an incredible hit, one
machines microcode can do x and y in parallel, machine z has hardware to
do operation w...  I think it would be good for a controller, or some compute
server that does one thing, but that is probably better done with a custom chip
or a coprocessor with that particular microcode built in from the start.
Doing something like this would then lead to virtual microcode, which I heard
something about once, but I don't think I'd ever want to see it in use.  I
think about the only use for something like this would be a lab machine to test
out different machine styles (ie. what would happen if  a 68000 had instructions
to... or can we do the same thing without...)  Well, that's my $0.02 worth,
and probably wrong too, I'd like to hear better/other ideas, but finals are in
5 days, and then this account goes away permenantly...


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