Article View: comp.arch
Article #11565Re: Atomic operations
From: Terry R. Friedrichsen
Date: Tue, 14 May 1991 14:59
Date: Tue, 14 May 1991 14:59
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While we're on this subject, can somebody give me a rundown on how locking primitives cam be implemented on the MIPS RISC chips? I know that load-linked (LL) and store-conditionally (SC) are the answer for the R6000, but what about the R2000 and R3000? AdTHANKSvance. Terry R. Friedrichsen terry@venus.sunquest.com (Internet) uunet!sunquest!terry (Usenet) terry@sds.sdsc.edu (alternate address; I live in Tucson) Quote: "Do, or do not. There is no 'try'." - Yoda, The Empire Strikes Back
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rutgers!gatech!ncar!noao!arizona!sunquest!venus.sunquest.com!terry From: terry@venus.sunquest.com (Terry R. Friedrichsen) Newsgroups: comp.arch Subject: Re: Atomic operations Summary: how-to on MIPS processors Keywords: atomic synchronization MIPS Message-ID: <19305@sunquest.UUCP> Date: 14 May 91 14:59:06 GMT Sender: news@sunquest.UUCP Followup-To: comp.arch Distribution: usa Organization: Sunquest Information Systems, Tucson Lines: 15