🚀 go-pugleaf

In article <28471@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov (Hugh LaMaster) writes:
>In article <199@dg.dg.com> uunet!dg!rec I wrote:
>>of compute power.  On the 88K, we need less than 1 MIPS to generate
>>a Dhrystone MIPS.  In other words, we get Dhrystone MIPS > CPU
>>clock speed.  When this first happened here, many people were
>Could you clarify what you mean? I know of no correlation between
>"Dhrystones/second" and "Instructions issued/second".
> ....
>  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
>  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
>  Moffett Field, CA 94035     
>  Phone:  (415)694-6117       

Before going any further, I would like to point out that I am (was) pointing
out anecdotal information.  When we first begain to run benchmarks on the
AViiON 88K products, we came up with Dhrystone numbers which when converted to 
VAX MIPS came out higher than the RAW MIPS of the machine.  The 16.67 Mhz 
machine has a peak raw MIPS rating of 16.67 MIPS (1 instruction per clock).
16.67 Dhrystone MIPS is 29289 Dhrystones/Second.  Since we were getting 
more Dhrystones/second than this, some people were suprized.

Hugh, I agree that Dhrystone is one benchmark in a whole field of
benchmarks.  However, I feel comfortable drawing a simple conclusion
from this result:  It is not clear that a CISC processor will take
FEWER INSTRUCTIONS to solve a problem than a RISC processor.  In some
cases RISCs may require fewer instructions.

This contrasts with some early claims that RISCs could execute 
short instructions in a shorter time than a CISC could execute long 
instructions doing the same work.  From then on, in some circle,
RISCs have been tacitly assumed to require more instructions to
do a given job than CISCs.

Robert Cousins
Dept. Mgr, Workstation Dev't.
Data General Corp.

Speaking for myself alone.