🚀 go-pugleaf

In article <19088@winchester.mips.COM> John Mashey writes:

>1) (OPINION): N overlapping chip designs for the same architecture
>are not necessarily better than one really good design, for the same reason
>that having N software teams doing the same job may (or may NOT) be as
>effective as having one really-experienced team doing a project.
>I observe that there are relatively few world-class, leading-edge, proven,
>high-performance VLSI microprocessor design teams around, who can do good
>architecture AND implementation.  Anybody who is trying to play in this
>game, with their own design, but without such a team is probably wasting
>their time.

And in article <19182@winchester.mips.COM> John gives the following excuse
for this article (the article he is replying to is <18154@cup.portal.com>
by Brian Case):

>>If John Mashey can post 300+ lines of marketing counter-measures, then I can
>>post a few lines about my OPINIONS too.
>
>>I think these discussions are very interesting, after all, I did read all
>>of John's posting, but they are nearly completely inappropriate for comp.arch,
>>IN MY OPINION.  Even the note that precipitated John's note was dicey.
>
>Well Brian is probably right on this [and I wouldn't have been as long,
>except I'd just been reading a Cypress brochure that claimed SPARC
>had "thousands of times more lines of code than all other RISCs put
>together." among other things that stirred me up.]

I'm afraid I'm going to have to use the same excuse as John for writing
this article.  After reading the first article above, I was also stirred
up.  John implies that MIPS has cornered the market on "world-class, 
leading-edge, proven, high-performance VLSI microprocessor design teams
around, who can do good architecture AND implementation."  I have to take
serious exception to this statement.  

First off, is MIPS a semiconductor company or systems company?  How can 
MIPS possibly suggest that they are "the" major force in silicon design 
and implementation if they are a systems house, and NOT a semiconductor 
house?  What sort of economic forces are going to force them to keep
their processor architecture and implementation state-of-the-art without
direct competition?  And by competition I don't mean companies who second
source your implementation, for they will not compete on architecture
or implementation, they will only compete on processing technology.
With SPARC, there are several (ie Texas Instruments, Fujitsu, LSI Logic,
Cypress Semiconductor (aka Ross Technology)) semiconductor houses working 
on advancing processing technology, architecture, and implementation.  
All of these companies have extreme economic incentives for working
diligently on advancing their products.  Yet, even with all of these 
different implementations of the SPARC architecture, you can take any
binary database and binary code and execute it on any system and it will
produce the same results.  This can NOT be said of systems which use the 
MIPS processor.  Because of the byte-sex difference between MIPSco
systems and DEC systems, it is NOT possible to take the same binary
database and code and get the same results on both systems even though
they both use the same MIPS processor!

As far as personnel goes, how can John possibly imply that MIPS has
cornered the market on experienced and proven microprocessor design
teams.  At Ross, we have no lack of experience in semiconductor 
architecture or design.  All of our personnel are members of the elite 
club you described (ie world-class, leading-edge, ...).  Ross Technology 
founders include the program manager/chief architect and the circuit 
design manager of Motorola's 88000 RISC processor.  Our design team 
has personnel with the following credentials:
-  Designers of the only commercially available 40Mhz RISC processor
   (Cypress Semiconductor's CY7C601).
-  Designers of the 68000 processor family (including the 68030 and 68040).
-  Designers of the 88000 processor family (besides the founders).
-  Designers of the 29000 processor.
-  Designers of a 100Mhz, 200 Mflop VHSIC CMOS processor with over 
   2,000,000 transistors (sorry, not a commercial part).
-  Designers of the Zilog Z8 microcontroller family.
Our design methodology includes state-of-the-art silicon compilation
technology, and our process is state-of-the-art 0.8u CMOS.
We have personnel who were offered positions with Intel's i860 group,
and with the Sun/TI processor group you alluded to, but who chose Ross
over these groups because of our state-of-the-art design methodologies
and design expertise.  (Do either of these groups or MIPS have anyone 
who chose them over Ross Technology?  I think not.)

Although I know very few members of the Sun/TI design team previously 
referred to, I know they have people with exceptional qualifications 
also, such as:
-  Program manager of the 80386 program.
-  Designers of the 80386.
-  Designers of the HP Precision Architecture.
Unfortunately, I don't know people at LSI Logic or Fujitsu or even
the vast majority at Sun working on SPARC and so can not comment on 
their accomplishments and qualifications, but maybe others reading 
this can.

I apologize for taking up comp.arch space with this article, but I
am a member of Ross's design team, and I take it personally when
people imply that me and my company lack the expertise needed to
design high-performance microprocessors.  I hope I have set the 
record straight on the quality of personnel implementing the SPARC
architecture at Ross Technology and elsewhere in the industry.

-steve studulski                      ross!steves@cs.utexas.edu
-ROSS Technology, 7748 Hwy 290 West Suite 400, Austin, TX 78736
   <As usual, I speak only for me, and not for my company>
-- 
-steve studulski                      ross!steves@cs.utexas.edu
-ROSS Technology, 7748 Hwy 290 West Suite 400, Austin, TX 78736
   <As usual, I speak only for me, and not for my company>