Article View: comp.arch
Article #1787Re: delayed branch
From: Tim Olson
Date: Wed, 09 Aug 1989 15:00
Date: Wed, 09 Aug 1989 15:00
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In article <0YrsEMy00V4GQ=CJZw@andrew.cmu.edu> jk3k+@andrew.cmu.edu (Joe Keane) writes: | The IBM RT manual says (rather verbosely IMHO): | | Certain instructions are not allowed to be the subject of a branch with execute | instruction. Since the branch with execute instructions change the normal | sequential execution of instructions, the subject instructions cannot be an | instruction that also changes the instruction sequencing; otherwise the | processor may be put in an unpredictable state. Thus, all branches, jumps, | traps, Load Program Status, Supervisor Call, and Wait instructions cannot be | subject instructions. The system processor provides hardware that detects | these illegal instructions and causes a program check interrupt if any of these | instructions occur as the subject of a branch with execute instruction. Thanks for the information -- I didn't have my RT arch. manual with me to look it up. Does anyone else know of other processors with such restrictions? -- Tim Olson Advanced Micro Devices (tim@amd.com)
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!watmath!att!ucbvax!amdcad!cayman!tim From: tim@cayman.amd.com (Tim Olson) Newsgroups: comp.arch Subject: Re: delayed branch Message-ID: <26676@amdcad.AMD.COM> Date: 9 Aug 89 15:00:12 GMT References: <828@eutrc3.urc.tue.nl> <26667@amdcad.AMD.COM> <0YrsEMy00V4GQ=CJZw@andrew.cmu.edu> Sender: news@amdcad.AMD.COM Reply-To: tim@amd.com (Tim Olson) Organization: Advanced Micro Devices, Austin, TX Lines: 20