🚀 go-pugleaf

In article <10544@cit-vax.Caltech.Edu> yair@tybalt.caltech.edu.UUCP (Yair Zadik) writes:
>A couple of years ago there was an article in Byte about a proposed design
>which they called WISC for Writeable Instruction Set Computer.  The idea
>was to do a RISC or microcoded processor which had an on board memory 
>containing macros which behaved like normal instructions (I guess it was
>on EEPROM like memory).  That way, each compiler could optimize the 
>instruction set for its language.  The end result (theoreticly) is that
>you get the efficiency of RISC with the memory bandwith of CISC.  I haven't
>heard else about it.  Is anyone out there working on such a processor or is
>it just a bad idea?

Yes, it is a bad idea.  In the mid 60's I was at Standard Computer (no longer
in existance) and I actually built such a machine.  It was called the
Standard EX01 (EX01 was for expermintal number 1).  The user could
dynamically alter the instruction set of the machine.  The machine was micro
coded and had a writable control store.  The 'basic' instruction set provided
a mechanism for writing to control storage.

In practice we found that it was impossible to make the thing work because
any modification to the control store could effect th 'basic' instruction
behavior.  As an example, one of the problems we found was that when running
the 'FORTRAN' instructions, double precision floating divide produced the
wrong answer if the instruction was executed at the same time as a tape unit
was reading a file mark.  I decided that there was no way to support a
machine like that in the field, so the experment was terminated.

   Marv Rubinstein