🚀 go-pugleaf

>In article <19463@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
>>	b) Load-misses (R3000s use write-thru caches, so there aren't really
>>		store misses).
>Since the R3000 uses write-thru caches and 
>since the depth of the write buffer is 4, 
>I assume that "stores" stall the processor only when more 
>than 4 consecutive writes occur or whenever the buffer overflows. 
>Saving the register file on a context switch could certainly
>generate stalls if it is done sequentially (i.e without interleaving
>register stores with non-store intructions).
>From your comment I suppose that those situations do not occur very often?
>
>					Marc Tremblay
>					marc@CS.UCLA.EDU
>					Computer Science Department, UCLA

What about block copies (like, copying I/O data from kernel to user)?
(SUNOS 4 mapped files reduce this a bit)

Sometimes there's no substitute for having a good, interleaved,
memory system (which I believe MIPS does(?))