🚀 go-pugleaf

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>In article <40718@bbn.COM> slackey@BBN.COM (Stan Lackey) writes:
>I strongly suspect the RISC guys are, as we speak, analyzing stuff like:
> What kind of sequences frequently show up
>Let me guess what they're finding.  Correct me if I'm wrong.
> (..lots of pairs that look like single CISC instructions...)
>Look familiar?  This prompted my first reaction when RISC started
>getting popular: Where do they go from here? Yes, it's an interesting
>technology opportunity.  But I'd rather implement the next generation
>machines as CISC's rather than RISC's, IF I HAVE TO STAY INSTRUCTION
>SET COMPATIBLE.  In other words, I think that when they learn how to
>implement a fast CISC, it will go faster than the same-technology
>RISC.  Why?  Because for the RISC to keep up, it will have to execute
>an average of two instructions per cycle, and one instruction is a lot
>easier to implement than two, even with auto-increment addressing.
>
>Of course, there is always the possibility to do what they did the
>first time: come out with a new architecture that matches the
>technology window exactly.  Note recent product announcements: this
>just keeps happening!  It's just that when you do this, expect a
>limited lifetime of the architecture.
>
>-Stan  [Disclaimer:  Do I have an opinion yet?]

Absolutely- maybe. I certainly agree that the current RISC philosphy is just
a window in time. As design tradeoffs change (and they will), a lot of what
currently is dogma will become rather obsolete. For example, just as compiler
technolgy affected our design choices, silicon compiler technology might affect
it. New device technologies (GaAs, new kinds of memory device) will affect the
relative speeds of memory versus logic. Advances in compiler technology may
take advantage of cache control operations to optimize cache hit ratios, or
be able to compiler for parallel machines.

I'm not sure, however, that you can with authority that it will be easier to
implement a CISC type mem-reg architecture than it would be to execute two RISC
style instructions at once (at the same speed), because the RISC approach lets
you schedule the interactions at compile time, while the CISC is forced to do
it at run time. Therefore, the RISC might keep up without going balls out for
speed.

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