🚀 go-pugleaf

In article <43445@bbn.COM> slackey@BBN.COM (Stan Lackey) writes:
>The TI 990/9900 did this - the CPU had a 'workspace pointer' which
>pointed to R0, the base of the register file, hopefully in a section
>of main memory that was implemented in Schottky RAM.
>
>Now would 40,000 other readers mind adding more architectures to the
>list?  Preferably really old ones.  :-)

How about the Zilog Z8 (not old enough).  It has 124 bytes of register
space and a "Register Pointer" that lets you define one of the 8 blocks
of registers as working registers which lets you get to them with smaller,
faster instructions.  The 16-bit instructions generally require a pair
of working registers for the address.  Nice machine for peripherals, modems,
etc.  I set up different register blocks with data for each interrupt routine,
so the interrupt code merely had to save RP.

An architectural issue - the Z8 convinced me that one of the key criteria
in choosing a processor (or designing one) is how general purpose the
general purpose registers are.

The Z8 is an eight bit machine, even more so than the Z80.  However, a 16
bit add was just two instructions:

	add	r4,r8
	adc	r5,r9

If you needed 32 bits, you need two more instructions:

	adc	r6,r10
	adc	r7,r11

Special purpose register architectures like the Z80 (or [gack] 6502) are a
pain to extend.  Even the 68000's dichotomy between the address and data
registers causes problems.  A Japanese company made a "68200" which was
patterned after the 68000 but with more general purpose registers.  We found
that we could write smaller, faster code for it instead of the 68000 thanks
largely to not having to shuffle data between the A and D set.

Of course (how can I let it slip by?), the PDP-10 is a general purpose register
machine.  I could write an instruction on it and feel as though I had
accomplished something.  Writing "mov d0,a0" makes me wish I had a PDP-11!


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