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Article #10504Re: RISC vs. CISC -- SPECmarks
From: Dik T. Winter
Date: Mon, 29 Apr 1991 20:52
Date: Mon, 29 Apr 1991 20:52
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In article <11412@mentor.cc.purdue.edu> hrubin@pop.stat.purdue.edu (Herman Rubin) writes: > The CYBER 205/ETA 10 is a vector pipeline machine, with the most versatile > vector architecture I know of. With slight modification, it would be able > to handle in a single instruction vectors of arbitrary length, and one does > not have to worry about alignment of vectors in vector registers. And now consider what occurs on a page fault in the middle of an instruction! A single vector instruction can create over 45 page faults. Still worse if you only run out of the (16) associative registers used to cache page table entries (half page faults?). -- dik t. winter, cwi, amsterdam, nederland dik@cwi.nl
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arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!uunet!mcsun!hp4nl!charon!dikReferences:
<1991Apr22.044553.16805@mp.cs.niu.edu> <TH_A6-F@xds13.ferranti.com> <11412@mentor.cc.purdue.edu>Show Full Headers
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!uunet!mcsun!hp4nl!charon!dik From: dik@cwi.nl (Dik T. Winter) Newsgroups: comp.arch Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: <3423@charon.cwi.nl> Date: 29 Apr 91 20:52:02 GMT References: <1991Apr22.044553.16805@mp.cs.niu.edu> <TH_A6-F@xds13.ferranti.com> <11412@mentor.cc.purdue.edu> Sender: news@cwi.nl Organization: CWI, Amsterdam Lines: 12