Article View: comp.arch
Article #22124Re: RISC Machine Data Structure Word Alignment Problems?
From: Phil Ronzone
Date: Fri, 02 Feb 1990 19:12
Date: Fri, 02 Feb 1990 19:12
23 lines
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1690 bytes
In article <AGLEW.90Jan31211451@dwarfs.csg.uiuc.edu> aglew@dwarfs.csg.uiuc.edu (Andy Glew) writes:
>>Having a microcoded unaligned data capability is faster than
>>user-level instructions doing the same thing.
>
>Why?
>
>Microcoded unaligned data takes two cycles to load an unaligned datum.
>(Assuming the unaligned datum overlaps two data bus widths.) MIPSco
>style load-left and load-right take two cycles to load the same
>unaligned datum.
I was thinking of bus-wide words (i.e., typically 32-bits).
You have at least:
BUS FETCH / SHIFT ALIGN / BUS FETCH / SHIFT ALIGN / OR / STORE
Implementing these at typical user level adds even more -- tests to
figure out how much to shift etc.
------Me and my dyslexic keyboard----------------------------------------------
Phil Ronzone Manager Secure UNIX pkr@sgi.COM {decwrl,sun}!sgi!pkr
Silicon Graphics, Inc. "I never vote, it only encourages 'em ..."
-----In honor of Minas, no spell checker was run on this posting---------------
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!rpi!brutus.cs.uiuc.edu!uakari.primate.wisc.edu!ames!sgi!shinobu!odin!maddog!pkr From: pkr@maddog.sgi.com (Phil Ronzone) Newsgroups: comp.arch Subject: Re: RISC Machine Data Structure Word Alignment Problems? Message-ID: <3518@odin.SGI.COM> Date: 2 Feb 90 19:12:27 GMT References: <111@melpar.UUCP> <1990Jan21.224826.1699@esegue.segue.boston.ma.us> <S4B1L47xds13@ficc.uu.net> <1871@l.cc.purdue.edu> <KMD168Axds13@ficc.uu.net> <3428@odin.SGI.COM> <AGLEW.90Jan31211451@dwarfs.csg.uiuc.edu> Sender: news@odin.SGI.COM Organization: Silicon Graphics, Inc., Mountain View, CA Lines: 23