Article View: comp.arch
Article #3039Re: RISC vs CISC (rational discussion, not religious wars)
From: Allen J. Baum
Date: Thu, 16 Nov 1989 22:13
Date: Thu, 16 Nov 1989 22:13
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>In article <5952@ucdavis.ucdavis.edu> lee@iris.davis.EDU (Peng Lee) writes:
>In article <TOMS.89Nov15114003@omews44.intel.com>,
>toms@omews44.intel.com (Tom Shott) writes:
>>
>> A novel architecture from the Computer Systems Group at UIUC published by
>> Dave Archer, et el used multiple task running on one CPU to hide delays.
>> For example w/ a 4 stage pipeline, the CPU chip would run four tasks at
>> once.
>One very interesting
>aspect I am currently looking at is possibility of implementing at
>semaphore in these register sets.
Not so novel; this scheme was used in the Denelcor HEP, and by Stellar in
their new machine. The Stellar had some kind of semphore feature so that the
parallel running tasks could communicate with each other. The HEP had a
semophore bit/memory location!
--
baum@apple.com (408)974-3385
{decwrl,hplabs}!amdahl!apple!baum
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!watmath!att!rutgers!ucsd!usc!apple!baum From: baum@Apple.COM (Allen J. Baum) Newsgroups: comp.arch Subject: Re: RISC vs CISC (rational discussion, not religious wars) Message-ID: <36564@apple.Apple.COM> Date: 16 Nov 89 22:13:41 GMT References: <TOMS.89Nov15114003@omews44.intel.com> <503@ctycal.UUCP> <15126@haddock.ima.isc.com> <5952@ucdavis.ucdavis.edu> Reply-To: baum@apple.UUCP (Allen Baum) Organization: Apple Computer, Inc. Lines: 23