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>In article <324@svcs1.UUCP> andy@svcs1.UUCP (Andy Piziali) writes:
>The ES-1 is different in that it delivers Cray class supercomputer performance
>without resorting to vector facilities by providing a moderate number of CUs
>for use by a like number of threads in a single parallel program.  The CUs may
>also be time-shared in a multi-user environment like a classical mainframe.

This is no different than many other multiprocessor with lotsa processors.
Many of the issues cited were implementation (crossbars, highly pipelined,
separate int, fp add, fp mult) rather than architectural.
The problem with  multiproceesor is to get my dusty decks running on them.
And, if you have no architectural support for this, just software, then anyone
could use the same technique and slap together a bunch of micros to achieve
the same end. So, what are the architectural features that permitted this
system to be used effectively?

Note that I'm not saying that a system as you described is trivial to build.
High preformance crossbars can be incredible mess; in fact, extremely difficult
to build without sacrificing latency. What was the latency though the crossbar
(i.e. how many delay slots were there after a load?)

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