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Article #20513

Re: i860 cache flushing

#20513
From: Lance Berc
Date: Sat, 25 Mar 1989 03:33
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The 30usec avg, 60usec worst case i860 cache flushing times did not include
the rest of the context switch. I believe that without save/restore of the
FPU a full switch is in the 60 - 90 usec range (this is mostly a guess).
Using John's 60 - 120 switch/sec guestimate we're still in the 1 - 2 percent
range, which should be acceptable in a multitasking situation.

Saving and restoring the FPU state is pretty hairy - the manual's example
has about one hundred instructions. The time required will depend heavily
on the memory subsystem characteristics since there probably won't be any
I or D cache hits here. Multitasking number crunching applications probably
isn't a good idea unless they are given larger timeslices. No surprise.
Lance Berc                lance@orc.olivetti.com      (415) 496-6248
Olivetti Research Center  lance%orc.uucp@unix.sri.com <standard disclaimer>
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References: <15888@winchester.mips.COM> <39485@oliveb.olivetti.com> <24958@amdcad.AMD.COM>

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From: lance@orc.olivetti.com (Lance Berc)
Newsgroups: comp.arch
Subject: Re: i860 cache flushing
Message-ID: <39722@oliveb.olivetti.com>
Date: 25 Mar 89 03:33:14 GMT
References: <15888@winchester.mips.COM> <39485@oliveb.olivetti.com> <24958@amdcad.AMD.COM>
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