Article View: comp.arch
Article #21730Re: VME Bus Standard
From: Desmond Young
Date: Thu, 14 Dec 1989 20:20
Date: Thu, 14 Dec 1989 20:20
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One comment, there is a group of (future) Futurebus+ users in Europe that have sent out fliers (should that be flyers?) encouraging people to join their effort to: "define useable subsets of Futurebus +". This does hint at the very (very) CISC nature of Futurebus+. It has every facility (almost) ever dreamt of. As an analogy to CISC processors, it almost has a single instruction to compile a program :-). (Well, a wee bit of an exaggeration). Anyway, if you want to go fast, it has too much baggage. My Opinion etc.
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arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!wuarchive!decwrl!nsc!voder!dtg.nsc.com!desReferences:
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!wuarchive!decwrl!nsc!voder!dtg.nsc.com!des From: des@dtg.nsc.com (Desmond Young) Newsgroups: comp.arch Subject: Re: VME Bus Standard Summary: Futurebus + Keywords: Futurebus, RISC Message-ID: <411@blenheim.nsc.com> Date: 14 Dec 89 20:20:36 GMT References: <7172@pt.cs.cmu.edu> <112400007@uxa.cso.uiuc.edu> <390@blenheim.nsc.com> Organization: National Semiconductor, Santa Clara Lines: 11