🚀 go-pugleaf

umh@vax5.cit.cornell.edu (Maynard Handley) says:
 
>Much as we all hate intel processors, it's always interesting to see what
>new perversions they come up with. Does anyone know what will make the 586
>different from a 486? Will it be just like 386->486, so some more cache and
>a little faster, or is there more to it than that?
 
Normally, Intel doesn't make their first announcement of new products on
Usenet, but I've been granted permission to answer your questions in
general terms.
 
Although from the programmer's point of view the software model of the 586
is an upward-compatible superset of the 486, the underlying implementation
is radically different, especially with regard to the cache.  While the
486 has a unified instruction/data cache, the 586 has separate caches for
the CS, SS, DS, ES, FS, and GS segments.  Although this does not significantly
accelerate code written for the "flat" model used by Unix and OS/2, more than
90% of all 86-family applications were written for an earlier model which
encouraged programmers to divide their memory references into independent
code, stack, and up to four data spaces.  These programs will benefit
enormously from the new "hex-cache" architecture.

A novel method has been developed for reducing the cost of floating-point
performance to the end user.  Each 586 has 100 bytes of EPROM for
storing passwords unique to each chip.  When a user decides to upgrade
to hardware floating point, he simply calls Intel and buys the password
for enabling the on-chip FPU.  Each password is good for 10 gigaflops,
i.e. you get 10,000,000,000 floating point operations.  (An 8-bit
password is sufficient, because three consecutive failed password attempts
permanently disables the FPU).  When you buy your 100th password, the FPU
becomes permanently enabled.  This benefits the consumer because it allows
him to buy exactly what he needs, rather than overspending on unused performance.
It also cuts out the middleman, allowing the end-user to reap the cost savings
of dealing directly with Intel.

A new native machine model, based on the i860, will be used.  Binary
compatibility with existing operating system software will be preserved
through the introduction of "virtual 386/486" mode, an execution mode
in which the 586 emulates the current model.

The pin configuration is footprint-compatible with the 486, however
compatibility with existing sockets was sacrificed in order to introduce
a new PGA package with 1 mm diameter pins.  The higher conductivity of
these pins is important for reducing on-chip power and ground noise. :-)