🚀 go-pugleaf

--------
[]
>
>>(3) Are there machines with both dynamic (windowed) and static (normal)
>>registers? For instance it might be useful for quick O.S. interrupts to
>>use only statics and not go to the trouble of setting up a register
>>window stack (which would involve lots of reads and writes moving the
>>old stack completely out to memory and then back again later).


Ditzel et. al. have finally published details of the CRISP processor,
which is a chip implements a stack cache with 32 registers. This
implementation appears to be a register window with variable overlap,
in effect. An entry instruction at the head of each procedure
allocates space in the 'register file', spilling to main mem. if
required. A cleanup instruction after return specifies how many top
of stack locations will be needed, and hardware will 'unspill' to
keep that many valid. The architecture is memory to memory... the
stack cache can be addresses as ordinary memory (but is obviously
faster), and can be byte addressed. They claim exceptional high hit
ratios on the stack cache, and performance of about 9x a VAX780
running at 16Mhz (for some number of benchmarks including PCC--
smaller benchmarks show 30x!). There are a number of other
architectural innovations, most importantly a zero cycle branch.
There are papers in both this weeks Compcon and ISSCC proceedings.

The interrupt is very simple. The PC, PSW, and a Interrupt ID get
pushed onto the interrupt stack. The stack cache, however, is still
addressed by the regular stack pointer; therefore all accesses will
go to main memory instead of the stack. If the interrupt code runs in
the same address space, simply changing the interrupt stack pointer
to be the same as the stack pointer suddenly gives you access to the
stack cache.

--
{decwrl,hplabs,ihnp4}!nsc!apple!baum		(408)973-3385