🚀 go-pugleaf

> >HP has been shipping 64 bit virtual address machines.  All of the above are
> >32-bit integer and IEEE compliant floating point machines.
> 1) can you say more about what this "Level x compliance" means?
> 	(Does that mean that you can build HP PA machines with 32/32, and that's	called Level 0?  or does it mean something other than compliance with
> 	an HP-internal spec?)

It means "compliance with the Architecture Control Document". The idea is
to allow a range of implementations from the single-board microcontroller
type (which probably doesn't need the full 64-bit address range) through
the midrange to the high end (which allows a full 64-bit address).

> 2) I suspect that the original question was looking for machines more like
> some supercomputers, i.e., with 64-bit integers and addresses that are
> used directly as such (which I don't think HP PA does: correct me if I'm
> wrong, but aren't there segment registers that can be controlled by the
> compilers, rather than 64-bit flat addresses?)

Well, it's true that declaring a pointer the usual way yields a 32-bit
pointer (a short pointer), but it's possible to declare full 64-bit
pointers and manipulate them as such. Yes, the address space is segmented
into 4GB segments, so no single object can be larger than 4GB (32 bits).

So you're right, there's no flat 64-bit address space, but it's possible to
have an awfully large data area in disjoint pieces. I know that the
original poster was enquiring about 64-bit flat spaces, and that this
machine does not quite fit that description. I'm just clearing a side
question.
---
Shankar Unni.