Article View: comp.arch
Article #22500Re: 64-bit addresses
From: Patricia Shanahan
Date: Wed, 21 Feb 1990 17:42
Date: Wed, 21 Feb 1990 17:42
21 lines
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1471 bytes
In article <29718@brunix.UUCP> phg@cs.brown.edu (Peter H. Golde) writes:
>One might note that implementing a 64-bit address space
>with 64 KB pages and 8 bytes/page in the page table requires
>2 billion megabytes of page-table space. Hmmmmm.....
>
>--Peter Golde
If the real memory is small compared to the address space, don't use page
tables. If you must use page tables, design them as sparse arrays.
If the real memory is large, you would probably want a bigger page
size anyway.
Those systems I am familiar with that seemed to have a good fit between
page size and memory size had the page size approximately the square root
of the memory size of a largish system. Anyone know of any counter-examples?
--
Patricia Shanahan
ps@fps.com
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phone: (619) 271-9940
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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!cs.utexas.edu!hellgate.utah.edu!helios.ee.lbl.gov!ucsd!ucsdhub!celit!ps From: ps@fps.com (Patricia Shanahan) Newsgroups: comp.arch Subject: Re: 64-bit addresses Message-ID: <6998@celit.fps.com> Date: 21 Feb 90 17:42:58 GMT References: <9708@spool.cs.wisc.edu> <20270@cfctech.cfc.com> <11112@encore.Encore.COM> <753@dgis.dtic.dla.mil> <WAYNE.90Feb11165528@dsndata.uucp> <3606@uceng.UC.EDU> <757@dgis.dtic.dla.mil> <4852@scolex.sco.COM> <29718@brunix.UUCP> Sender: daemon@fps.com Reply-To: ps@fps.com (Patricia Shanahan) Organization: FPS Computing Inc., San Diego CA Lines: 21