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Article #1853Context-switch times
From: Gideon Yuvall
Date: Wed, 16 Aug 1989 23:02
Date: Wed, 16 Aug 1989 23:02
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What is a realistic context-switch penalty for the MIPS, SPARC, 88K, i860 (...) RISC chips? I'm looking for the number of cycles needed to do the task-switch, PLUS the penalty due to the new starting starting out with an "empty" cache. Thanks -- Gideon Yuval, gideony@microsof.UUCP, 206-882-8080 (fax:206-883-8101;TWX:160520)
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.csd.uwm.edu!cs.utexas.edu!uunet!microsoft!gideony From: gideony@microsoft.UUCP (Gideon Yuvall) Newsgroups: comp.arch Subject: Context-switch times Message-ID: <7408@microsoft.UUCP> Date: 16 Aug 89 23:02:16 GMT Reply-To: gideony@microsoft.UUCP (Gideon Yuvall) Organization: Microsoft Corp., Redmond WA Lines: 8