🚀 go-pugleaf

In comp.arch, jfc@grouse.dsg.dec.com (John F Carr) writes:

> In article <1992Dec14.072942.21962@doug.cae.wisc.edu>
> 	keiths@cae.wisc.edu (Keith Scidmore) writes:
> 
> >1)  I read that the 21064 divide unit is not pipelined and takes one cycle 
> >    per bit to produce a result.  Isn't this going to kill floating point
> >    performance? [...] I'm
> >    lead to think that DEC isn't interested in the FP performance of this chip,
> >    or do I have my facts wrong?
> 
> A double precision floating point divide is slow, but look at the benchmark
> results: the Alpha AXP 10000 is rated at 200 SPECfp92.  If you buy the
> low-end model you get 112 SPECfp92.  Obviously divide performance isn't
> critical to this large selection of real-world applications.

Quite right, SPECfp92 is not very sensitive to divide or square root
latency.  Which applications are?  Possibly 3D graphics.  Perhaps Mr.
Scidmore's applications are sensitive to divide latency since he
brought it up?  I don't know.

> In any case, considering the clock speed difference between Alpha AXP and
> competitive systems you are better off counting nanoseconds instead of
  ^^^^^^^^^^^^^^^^^^^

  That's right, you should compare latencies in nanoseconds, not cycles.
  I'll add an HP machine to your table.

> 			DEC Alpha AXP			IBM RS 6000
> 		 	133 Mhz	150 Mhz		 	41 Mhz	62.5 Mhz
> 			cycles	ns	ns		cycles	ns	ns
> FP mult or add	 6	 45	 40		 2	 48	 32
> FP divide		63	473	420		20	480	320

  			   HP 735
			   100 MHz
			cycles	ns
  FP mult or add	 2	 20
  FP divide		15	150


- Will Walker
  my own opinions