🚀 go-pugleaf

In article <HAMMAMI.98Feb25173030@pross113.u-aizu.ac.jp>,
Omar Hammami <hammami@u-aizu.ac.jp> wrote:
>
>
>Hi:
>
>I will appreciate to have pointers/references on analytical models
>developped for ILP CPUs (performance evaluation purposes).Thanks.
>
>O.H.
>
>

I don't know whether this is of interest to you or not, but here goes...

About 8 years ago I was involved in cache/memory subsystem modeling for
telephone switching computers.  Most of this stuff was based on the high-end
MC680__ family.  I modeled the CPU as a bus interface unit (essentially, a
queue) and an execution unit (a single server).  The model took into account
instruction cache hit ratio (derived via trace-driven simulation), memory
cycle time, (bus) clock frequency, and an instruction mix (derived from
analysis of call processing code running on one of these computers).  The
model correctly predicted sustained MIPs and determined where the
memory/processor performance limitations were.  A variation of this model was
used to analyze a proposed ultra-high reliability computer for a major
switching system.  The model took into account cache hit ratio, instruction
mix, mean MIPs given the EU was busy, memory cycle time, DMA interference,
cache miss update times, and made some reasonable engineering assumptions
about the hardware organization.  Lab data showed the model to be "accurate
enough for engineering purposes" (it was actually much more accurate than
that).

Both models were Markov chain based and could be easily implemented on a PC of
that vintage (the first one was actually run on an ancient "slide rule
calculator" -- it took a few minutes to run, but provided endless
entertainment for some of the hardware engineers who commented about their
years in graduate school).

Regards,

Bohdan Bodnar
bbodnar@lucent.com