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Article #7

Silicon compilation to FPGAs?

#7
From: Michael Gschwind
Date: Tue, 18 Jan 1994 08:10
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We are embarking on a project where we expect to do silicon
compilation targeted to Xilinx FPGAs. We have both Racal-Redac and
Synopsys here, but we don't really know which one to choose to do VHDL
synthesis. What are the pros and cons of both tools. Since we don't
really want to have to handle two tools, we'd like to hear from
anybody who has had experience with either of these tools. 

Answers to the following questions and any other kind of info/rumor/gossip
etc. concerning these tools will be appreciated:
How fast is the compilation? 
How stable are the tools? 
How effectively can you influence compilation strategies? 
Did you target to FPGAs or a different technology?
How efficient is the generated layout?
Did the compiler generate a functionally correct layout?
What other tools where necessary to fully simulate the design and
generated a bit stream? Xilinx tools? Viewlogic?
Caveats?

ThanX in advance,
mike
--

Michael Gschwind, Institut fuer Technische Informatik, TU Wien
snail: Treitlstrasse 3-182-2 || A-1040 Wien || Austria
email: mike@vlsivie.tuwien.ac.at  note: real time != real fast
phone: +(43)(1)58801 8156	   fax: +(43)(1)569 697
Ah! la vida es una fiesta, es surf, es playa, es calor,...
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From: mike@vlsivie.tuwien.ac.at (Michael Gschwind)
Newsgroups: comp.cad.synthesis,eunet.esprit.eurochip,comp.lsi
Subject: Silicon compilation to FPGAs?
Date: 18 Jan 1994 08:10:31 GMT
Organization: TU Wien
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