🚀 go-pugleaf

We are writing a new guide for Verilog designers called "Top Verilog Problems & How To
Solve Them." The book will be available later this year.

Here's the fun part: we will give a FREE copy of the book anyone who contributes a
problem/solution or useful story. It's simple:

1. Send me an email with the problem you encountered, and how you solved it. You can
also send an interesting Verilog anecdote.

2. Tell me whether you want attribution ("contributed by Joe Shmoe at XYZ Co.") or not.
We're happy to make it anonymous if you want.

3. Be sure to include the address where you want us to send your FREE book.

Examples:

"One of the most difficult problems I have had to solve is modeling an ABC circuit. The
challenge is the timing... Here's what we did..."

"We once spent three days trying to figure out why Verilog couldn't handle a relatively
simple design..."

That's it! Please send me email if you have any questions. Please do not respond to the
list.

Thanks!

Jake Kelly
TACTICS
phone +1 408-298-2200
email jake@tactics.com