🚀 go-pugleaf

Hi, 

and thanks for your replies on my posting on how to generate
a clock tree automatically. Several people were interested in
the results, so here is a summary:

The Synopsys design_analyzer has no feature to generate a
clock tree. There are scripts from the ESNUG (216 Item 1,
219 Item 1) to build a buffer tree; I'll try them out soon. 
 
Generating the clock distribution network in combination with 
placement and routing promises a more exact result because 
wire capacitances and the location of the flipflops on the chip 
can be considered. There is a feature called Clock Tree Synthesis 
in Cadence Cell3 / GateEnsemble, but it requires an additional 
license and costs extra. I was suggested to check out some other
CAD vendors' tools too, but as a university we can't afford that.

Some people from other (european) universities wrote that they
had to build a clock tree for their design manually. I hope to
avoid using a layout editor - our aim is a design flow with as
much synthesis as possible.

Bye, Martin.

--
Martin Radetzki, Universitaet Oldenburg, FB Informatik
Abteilung Entwurf Integrierter Schaltungen
email: martin.radetzki@informatik.uni-oldenburg.de