who handles synchronous bandwidth ?

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#170

From: Gopal Agrawal
Date: Tue, 08 Sep 1992 22:47

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While going through the data books of the AMD and National Semiconductor
chip sets for FDDI, I noticed that while AMD provides a register (TSYNC) 
in its MAC chip (for SAS) to represent the synchronous bandwidth, the N.S. 
chips don't. They just say that it is up to the user to assure that the 
synchronous frames queue does not take longer than the allocated bandwidth 
to transmit. Does the latest version of SMT say where exactly the 
synchronous bandwidth is to be handled. I mean, are there any registers 
or memory locations in the SMT or MAC or any other layer which are responsible 
to time the transmission of the synchronous frames ? 

How do the stations agree on the distribution of the bandwidth amongst 
themselves ?

regards,
--   
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Path: arc1-ca.pugleaf.net!sparky!uunet!cs.utexas.edu!tamsun.tamu.edu!gagrawal
From: gagrawal@cs.tamu.edu (Gopal Agrawal)
Subject: who handles synchronous bandwidth ?
Message-ID: <1992Sep8.224744.18743@tamsun.tamu.edu>
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Organization: Computer Science Department, Texas A&M University
Date: Tue, 8 Sep 1992 22:47:44 GMT
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