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Article #1855

FDDI cmt signal bits question

#1855
From: art wittmann
Date: Tue, 26 Jan 1993 21:02
25 lines
1588 bytes
If I do a "show interface", I get the following as part of the response.

  Phy-A state is active, neighbor is B, cmt signal bits 08/20C, status ILS
    Brk 119, Con 113, Tra 6, Nxt 1243, Sig 1130, Join 113, Vfy 113, Act 113
  Phy-B state is active, neighbor is A, cmt signal bits 20C/208, status ILS
    Brk 121, Con 121, Tra 0, Nxt 1320, Sig 1200, Join 120, Vfy 120, Act 120

On Phy-B, the signal bits indicate that both macs are on output.  This 
seems wrong to me, is it?  I don't think this is a cabling issue, but possibly
an implementation issue.  The device on the other side of Phy-B is a 
cresendo concentrator.

Problem is, we seem to be getting spurious ring_ops, sometimes many thousands 
in a row.  So far this is the first problem that I've found.

Any insight is appreciated.

Art

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Art Wittmann                                  Phone: (608) 263-1748
Associate Director                            Email: wittmann@engr.wisc.edu
Computer Aided Engineering Center                or: wittmann@cae.wisc.edu
University of Wisconsin, Madison
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From: wittmann@engr.wisc.edu (art wittmann)
Subject: FDDI cmt signal bits question
Organization: College of Engineering, Univ. of Wisconsin-Madison
Date: 26 Jan 93 15:02:52 CST
Message-ID: <1993Jan26.150252.2160@doug.cae.wisc.edu>
Originator: wittmann@muskie.engr.wisc.edu
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