🚀 go-pugleaf

As you may recall, On 6 Aug 92 05:00:00 GMT, Michael.Malak@halluc.com (Michael Malak) said:

Michael> I found the recent article in the August/September issue of Circuit
Michael> Cellar Ink about DSPs vs. RISC very interesting.  In it the i860 is
Michael> benchmarked as being the fastest at 96-tap FIR filtering. [...]

This is believable. The 860 has an 8Kbyte on-chip cache (like the 486, I think)
and this is a nice place to store filter coefficients (taps).  Additionally, the
floating-point side of the 860 is essentially a 3-stage multiply pipeline
followed by a 3-stage add pipeline. So you just do 3 points at a time and you
can make a real-valued FIR filter scream. (Complex is quite a different story -
three-stage pipelines make things messy).

Michael> Does anyone have any information about how fast the i860 can do an FFT,
Michael> either theoretical or measured?  I'm especially interested in how it
Michael> compares against the C30, the 96000 and the 56001.  Because since there
Michael> don't seem to be any 386 or 486 motherboards out there with DSPs on
Michael> them, the one from Happauge with the i860 on it might be worth a look.

In the 860 bible (i860 Microprocessor Architecture by Neil Margulis), the author
codes an FFT which achieves 57/80 MFlops. This is not really what the beast is
designed to do, IMHO. Seems I'm always writing 3 different versions of the same
routine - one for extremely short vectors (throw everything in registers), one
for medium-sized "if it all fits in cache" vectors, and one for long vectors
that use pipelined memory loads, bypassing the cache because they would just
thrash. I suspect I'd wind up doing much the same if I were coding an FFT, which
I haven't [as yet] had to do.

Hope this helps.
--
        Alan J.Stein    MIT/Lincoln Laboratory    alans@ll.mit.edu

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