Article View: comp.dsp
Article #1236state-of-the-art FFT processors
From: Gary D. Shiflett
Date: Fri, 09 Oct 1992 19:17
Date: Fri, 09 Oct 1992 19:17
23 lines
1061 bytes
1061 bytes
I am working on a project to determine the feasibility
of developing an ultra-high speed FFT signal processor subsystem.
My questions are:
1) What is considered state-of-the-art in FFTs?
2) Who are the players?
3) Has or is DARPA supporting the development of
GaAs FFT processors as part of a technology
enhancement initiative? With whom? Details?
4) Does anyone know of any POCs for FFT work at
nChip in San Jose, CA?
Thanks in advance,
--
Gary Shiflett
Applied Physics Laboratory
Johns Hopkins University
gary_shiflett@jhuapl.edu
Technical Details
Message-ID:
<1992Oct9.191713.19305@aplcen.apl.jhu.edu>Path:
arc1-ca.pugleaf.net!sparky!uunet!haven.umd.edu!darwin.sura.net!aplcen.apl.jhu.edu!newsShow Full Headers
Complete Article Headers
Newsgroups: comp.dsp Path: arc1-ca.pugleaf.net!sparky!uunet!haven.umd.edu!darwin.sura.net!aplcen.apl.jhu.edu!news From: shif@aplpy.jhuapl.edu (Gary D. Shiflett) Subject: state-of-the-art FFT processors Message-ID: <1992Oct9.191713.19305@aplcen.apl.jhu.edu> Keywords: digital FFTs, GaAs, DARPA Sender: news@aplcen.apl.jhu.edu (USENET News System) Organization: Johns Hopkins University Applied Physics Lab Distribution: usa Date: Fri, 9 Oct 92 19:17:13 GMT Lines: 24