🚀 go-pugleaf

hanke@nessie.cs.id.ethz.ch (Norbert Hanke) writes:
>In article <0WV1D7H@obh.in-berlin.de> nummer_5@obh.in-berlin.de (Christian Wierzbicki) writes:
>>I've read in Motorolas Hardware Manual on the 56001 that there has to
>>be fast static ram connected to the processor.
>>Therefore my questions are:
>>1.) How fast must this s-ram be at minimum (for usw with a 2MHz 56001)

>The access time of the s-ram has to be, without address decoding of any
>kind, about 55 ns. With address decoding accordingly less, you end up
>using 35 ns s-rams in most cases.

... assuming, of course, you want a zero wait state system.
However,  the 56001 can be configured with up to 15 wait states, which
will enable the use of much slower memory.
--
                                   * * *
Gord McGonigal                                  mcgonig@eeserv.ee.UManitoba.ca
Dept. of Electrical & Computer Engineering
University of Manitoba, Winnipeg, CANADA (R3T 2N2)       phone: (204) 474-6295