State-of-the-Art ADCs?

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Article #1982

#1982

From: Gary D. Shiflett
Date: Tue, 28 May 1991 16:46

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     I am working on a project to determine the feasibility
of developing an ultra-high speed FFT digital signal
processor. The notional requirements for the A/D converter
subsystem are 360 million complex samples per second (or
720 real MSPS) at 7 effective bits. My questions are:

     1) What is considered state-of-the-art in ADCs?

     2) Who are the players?
  
     3) Which is the preferred sampling architecture, e.g., 
        direct, analog or digital quadrature, analog or 
        digital Hilbert, at these rates and why (general)?

     4) Does anyone know of any POCs for ADC work in the 
        Advanced Circuits Technology Group at Hughes (El
        Segundo)?

     Thanks in advance,

--
Gary Shiflett
Applied Physics Laboratory
Johns Hopkins University
shif@aplpy.jhuapl.edu

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From: shif@aplpy.jhuapl.edu (Gary D. Shiflett)
Newsgroups: comp.dsp
Subject: State-of-the-Art ADCs?
Summary: Questions wrt ADCs
Keywords: digital sampling, analog-to-digital conversion
Message-ID: <1991May28.164628.25109@aplcen.apl.jhu.edu>
Date: 28 May 91 16:46:28 GMT
Sender: news@aplcen.apl.jhu.edu (USENET News System)
Organization: Johns Hopkins University Applied Physics Lab
Lines: 26