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Article #461DSP56001 timing query
From: Mark James
Date: Tue, 17 Oct 1989 00:40
Date: Tue, 17 Oct 1989 00:40
10 lines
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646 bytes
Is it guaranteed that external memory accesses by the DSP56001 will be separated by a whole number of instruction cycles (i.e. 0,1,2..) when running with zero wait states or is it possible that the gap could be 1/2, 1 1/2, 2 1/2, ... cycles. Thank you. Mark James mrj@basser.cs.su.oz
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!munnari.oz.au!basser!mrj From: mrj@basser.oz (Mark James) Newsgroups: comp.dsp Subject: DSP56001 timing query Keywords: DSP56001 hardware Message-ID: <2646@basser.oz> Date: 17 Oct 89 00:40:44 GMT Organization: Dept. of Comp. Science, Uni of Sydney, Australia Lines: 10