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Article #593Re: I860 fft performance
From: Ravi Rao
Date: Wed, 12 Aug 1992 18:51
Date: Wed, 12 Aug 1992 18:51
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In article <1992Aug6.125445.10704@nntp.nta.no> hlj@hal.nta.no writes: > >If the following two conditions are met: > > 1. All your data occupies less than 8 kbytes (such that all data > is in the cache or in registers) Obviously, you don't know about the existence of the nex-gen 860 which has 16K of data/instr cache. There are some other instr enhancements like 'pfld.q' to make use of full b/w. > 2. Your algorithm is such that it can be implemented in i860 > pipelined mode (which is awkward to program) To get peak performance, you have to program most uP in assembly language. There is no doubt that the i860 pipeline is hard to follow, but once you get the hang of it, its fairly easy.............. > >***** hlj@hal.nta.no (Harald Ljo"en) expressing his private opinions ****** -- ____________________________________________________ Ravi S. Rao SP1-82 Intel Corpn, Chandler, AZ e-mail: rrao@hopi.intel.com, rrao@pima.intel.com ____________________________________________________
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Path: arc1-ca.pugleaf.net!sparky!uunet!iWarp.intel.com|inews!pima!rrao From: rrao@pima.intel.com (Ravi Rao) Newsgroups: comp.dsp Subject: Re: I860 fft performance Message-ID: <12948@inews.intel.com> Date: 12 Aug 92 18:51:05 GMT References: <713099311.0@halluc.com> <1992Aug6.125445.10704@nntp.nta.no> Sender: news@inews.intel.com Organization: Intel Corp, Chandler, AZ Lines: 29