🚀 go-pugleaf

In article <12948@inews.intel.com> rrao@pima.intel.com (Ravi Rao) writes:
| In article <1992Aug6.125445.10704@nntp.nta.no> hlj@hal.nta.no writes:
| >
| >If the following two conditions are met:
| >
| >	1. All your data occupies less than 8 kbytes (such that all data
| >	   is in the cache or in registers)
| 		Obviously, you don't know about the existence of the nex-gen
| 		860 which has 16K of data/instr cache. There are some other
| 		instr enhancements like 'pfld.q' to make use of full b/w.
	Hmmm, seems like DSPs or RISC uPs which can efficiently access external
	memory (low access latencies and burst modes, >1 i/o bus for DSPs)
	would have an advantage over large *expensive* on-chip caches.  Just
	how expensive is this new gen 860? ;v)

| >	2. Your algorithm is such that it can be implemented in i860
| >	   pipelined mode (which is awkward to program)
| 		To get peak performance, you have to program most uP in 
| 		assembly language. There is no doubt that the i860 pipeline
| 		is hard to follow, but once you get the hang of it, its fairly
| 		easy..............
	860 programs must be hand-coded to get anywhere near stated
	performance.  Most RISC processors (the 860 is a VLIW uP, *not* RISC)
	perform quite well using compiled C.  For DSP, RISC can be easily hand
	programmed - the superscalar varieties even do the scheduling (with
	small scale optimizations) for you (unlike the 860).

Disclaimer:  I speak for myself and no one else - hell, I don't even work with
the Am29050 floating point RISC microprocessor any more.
--
Paul R. Teich                          pteich@cayman.AMD.COM
Advanced Micro Devices, Inc.           Direct 1-512-462-4268
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