🚀 go-pugleaf

Re; getting fast 56k memory write cycles (also re: obscure manuals)

My 4 cycle example was:
	4 cycle example	
		movep	Y:(r0)+,X:M_PBD

Michael van Elst - mlelstv@specklec.mpifr-bonn.mpg.de 
Replied 

	The movep instruction like all instructions with an absolute address
	need 4 clocks as the address becomes available after instruction 
	decoding.  For a 2 clock access you need the address in a register. 
	Since you use autoincrement, you probably try to write multiple words 
	in a loop.

	move #buffer,r0
	move #x_mpbd,r4
	move y:(r0)+,a
	do #buflength-1,_loop
	move y:(r0)+,a a,x:(r4)
_loop
	move a,x:(r4)
---

Thanks!,
	This works fine! This also points out another weak point in the
56k manual - it does not really go out of it's way to mention what state 
(before of after) the ACC registers are read durring parallel moves that also 
use the ACC. In the above case the a,x:(r4) ACC value preceeds the y:(r0)+,a 
move - this makes some sense - but if the op code were say lsr a  a,x:(r4) - 
then it is less clear [a,x:(r4) gets the ACC value before the shift - I
had to try it.  ]

	[ If anyone from Motorola is listening the manual could REALLY use some 
help in this area - ex: why repeat dozens of warnings about register R and N 
delays for every op code yet fail to mention the likely more important the 
implications of the ACC delays in parallel moves ? Have a dedicated
section devoted to inter-register/bus delays for all key operations just
preceding the opcode section could cut the manual down to about half the 
size - ex: by using references to it rather then cut and paste replication
of warnings. ]

# Mike Gore, Technical Support, Institute for Computer Research
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