🚀 go-pugleaf

Hello, world. How are everybody doing?

I've encountered a problem with the TMS320C30 bus a while
ago and I would like to discuss it with everyone.

The TMS320C30 has two buses. The primary bus and the expansion
bus. I designed my DSP board to operate the expansion bus with
MSTRB, which means the timing of the expansion bus and the primary
bus are the same. I put all my memories on the primary bus
and all the input/output on the expansion bus. 

Everything works fine until I start to test the decoded IO ports
on the expansion bus. The primary bus were running at zero wait
state at 32Mhz. The expansion bus were programmed at seven wait
states. (I have some slow IO to do so it seems the easy way to
slow down the bus. I was so wrong.) 

I first test the board with 5Mhz and every timing seems to be
fine. I put a read and a write port inside a endless loop to
verify the timing. It works fine until I put the board into
18Mhz. Then the read cycle is completely disappeared. The only
signal appears on the MSTRB and XR/W is the write cycle. I try
to put various NOP before and after the read and write since I
suspect I've got a register conflict somewhere. In several 
occusions, the bus cycles are completely gone, no MSTRB appears
on my scope.

As it turns out, I can not run the expansion bus slower than the
primary bus as long as I am running my program on the primary
bus. In 32Mhz, both bus has to operate on 1 wait state in order
for the expansion bus to operate properly. (You can have them
in zero wait state but only at 18Mhz. That is the speed I test
that works.) 

I suspect that there is intrinsic problem on the chip itself.
It is no longer cycle dependent when one bus operate faster
than another bus while the CPU has to interleave access them
both like running the program on the primary bus and doing
IO on the expansion bus.

If somebody has similar experience, I would love to hear from
you. The TMS320C30 is very powerful but not the easiest chip
to design with.

				simpson@kingcong.uwaterloo.ca
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