🚀 go-pugleaf

This is posted for Robert Bernecky (rbe@yrloc.ipsa.reuter.com), who
wrote the following:

a. In any of the S/370s I have used (any of them up to the 3084),
   ICM timed slower than L/LTR, EVEN WHEN there was no other instruction
   between the L and the LTR. 

   This is similar to MCVL/CLCL vs MVC/CLC loops (when you didn't need 
   the overlap case, which we often did in APL), where the page or so
   of code to setup the MVC/CLC loop and the final/first EX Rx,doclc
   usually ran about TWICE as fast as the single MCVL/CLCL instruction.

   It made a RISC convert outa me, it did, it did...

b. I suspect that if you could schedule the L/LTR properly by moving
   the L earlier (or the LTR later) in the instruction stream, they
   would run even faster than ICM. 

c. ICM can't be indexed, which makes it even lousier than L/LTR.
   I would have preferred LC (Load Character) and IB (Insert Bits).
   See B5500 book. Sigh.