🚀 go-pugleaf

On Sun, 26 May 91 14:20:00 PDT Leonard D Woren said:
>Hmmm... And I thought that the 360/91 was the only machine that had
>those blasted imprecise interrupts.  NOPR ^0 was a special
Did some poking around in my S/370 POO (GA22-7000-10) and
the "imprecise interrupt" on a store is listed in the "Priority of
program-interruption conditions" on page 6-32, so at least some
models of the S/370 may have had this problem.  I think that they fixed
this in the 303x, and later CPUs, so it was confined to the S/360 and S/370
processors only.

I see that what goes around, comes around..  sounds like the 360/91 had
similar pipelining and delayed branch semantics as the current
generation of RISC chips.  This proves that programmers as a whole are
getting soft - the 360/91 was considered programmable in assembler, but
today's programmers think that it's "too hard" and let an optimizing
compiler do it.....

/Valdis