Re: VMCF

Article View: comp.lang.asm370

Article #884

#884

From: Okan BEKATLI
Date: Wed, 13 Jan 1988 16:26

5 lines
743 bytes

Steve,
Before loading the wait PSW(and before or after authorizin VMCF),
set bit 31 of Control Regizter 0 to a value of 1.This setting is necessary
for receiving VMCF(Code X'4001') external interruptions.
Okan

Technical Details

Message-ID: <8801131625.AA08809@jade.berkeley.edu>

Path: arc1-ca.pugleaf.net!utzoo!utgpu!water!watmath!clyde!rutgers!sdcsvax!ucbvax!TRITU.BITNET!OKAN

References: <SCOTTY@UOGUELPH>

Show Full Headers

Complete Article Headers

Path: arc1-ca.pugleaf.net!utzoo!utgpu!water!watmath!clyde!rutgers!sdcsvax!ucbvax!TRITU.BITNET!OKAN
From: OKAN@TRITU.BITNET (Okan BEKATLI)
Newsgroups: comp.lang.asm370
Subject: Re: VMCF
Message-ID: <8801131625.AA08809@jade.berkeley.edu>
Date: 13 Jan 88 16:26:57 GMT
References: <SCOTTY@UOGUELPH>
Sender: daemon@ucbvax.BERKELEY.EDU
Reply-To: IBM 370 Assembly Programming Discussion List <ASM370%UCF1VM.bitnet@jade.berkeley.edu>
Distribution: inet
Organization: The ARPA Internet
Lines: 5
X-Unparsable-Date: Wed, 13 Jan 88 16:21:49 SET

Reply to Parent Message