🚀 go-pugleaf

In article <3910001@hpvcla.HP.COM> neff@hpvcla.HP.COM (Dave Neff) writes:
>The new HP "RISC" machine ... has 32 general purpose registers ... [and] up
>to 16 parameters [may be] passed ... via registers.  In my opinion much of
>the performance benefits of this architecture come from ... many general
>purpose registers and compilers [which] do excellent optimization.

That's probably true; the pdp-10 takes great advantage of "registered"
parameters, especially for monitor calls.  I've been thinking of an extended
LS (large system) architecture with word sizes of 48, 60, or 72.  LSX machines
may never be built, but they are interesting to think about.

The basic instruction format for the pdp-10 is:

     -----------------------------------------------------------------------
    |       op        |  ac   |@|  ix   |             base-addr             |
     -----------------------------------------------------------------------
     0      ...      8 9 ...12   14...17 18              ...              35

_op_, 9-bits, allows 512 operations (365 implemented ca '67, more since);
_ac_, 4-bits, specifies source/destination register; _@_, 1-bit, supports
indirect addressing (LS was intended (ca '65) as a giant LISP machine);
_ix_, 4-bits, supports indexed addressing; and _base-addr_, 18-bits,
specifies a local address (relative to the current section).

With this format (a 9-bit op-code, an indirect bit, two reserved(!) bits,
(n/4)-6-bit register addresses, and half-word local addresses), we get:
	  64 registers and    16M addresses for 48-bit words,
	 512 registers and  1024M addresses for 60-bit words, and
	4096 registers and 65536M addresses for 72-bit words!

Oh, what fun!  Wrap it up!  I'll take it!

Lum Johnson  lum@ohio-state.arpa  ..!cbosgd!osu-eddie!lum